Multi-Core Computer Architecture | Week 8

Session: JULY-DEC 2023

Course Name: Multi-Core Computer Architecture

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q1. Which one of the following statements is FALSE?
Write propagation ensures that a write is eventually seen by all the threads.
Memory consistency provides local ordering of accesses to all words in a cache block.
Cache coherence provides local ordering of accesses to each cache block.
Write serialization ensures that writes to the same location are globally ordered.

Answer: Memory consistency provides local ordering of accesses to all words in a cache block.

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Q2. What is the purpose of Write Propagation in memory consistency and cache coherence?
It delays write operations to ensure coherence
It ensures that the value written in one cache is propagated to at least one sharer in a predetermined order.
It guarantees that a write is eventually seen by all threads.
It blocks propagating the write values to other threads to ensure coherence.

Answer: It guarantees that a write is eventually seen by all threads.

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q3. Which one of the following protocols ensures that a cache controller sends broadcast messages in a common medium for other cache controllers connected to it for taking appropriate cache coherence operations?
Write serialization protocols
Snoopy protocols
Directory based protocols
Consistency protocols

Answer: Snoopy protocols

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q4. Consider a MESI cache coherence protocol. The cache controller of processor P2 snooping on the bus receives a broadcast message that processor P1 encountered a read miss on a cache block B that is in M state in P2. Apart from forwarding the copy of B to P1, what will be the state transition done by P2 on the cache block B?
Retain the state of B as M.
Change the state of B to S.
Change the state of B to I.
Change the state of B to E.

Answer: Change the state of B to S.

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q5. Which of the following are the advantages of using a directory based cache coherence protocol over a snooping based cache coherence protocol?
Reduced cache size requirements for a given workload
Less contention in accessing the directory
Elimination of broadcast messages
Scalability of processors attached to the interconnect

Answer: C, D

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q6. If two co-operating processors P1 and P2 write to two different words W1 and W2, respectively of a cache block B. The system uses directory cache coherence protocol. Which of the following statements is/are TRUE?
If memory accesses of P1 to W1 and P2 to W2 are strictly interleaved, then there will be no coherence misses at all.
There exists a false sharing of block B between P1 and P2.
There exists a true sharing of block B between P1 and P2.
If memory accesses of P1 to W1 and P2 to W2 are strictly interleaved, then the cache block B keeps bouncing between P1 and P2.

Answer: B, D

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q7. Consider a directory based coherence system for a 256 GB physical address space. A 16-core processor is connected to this physical address. Each core has a 128 KB, 4-way set-associative private cache memory of block size 256 bytes. Assume that the central directory will store information of most frequently used 1024 cache blocks only. Each directory entry will store the state (2 bits to represent one of the 3 states : E, U and S), block number and list of shares (1-bit per core). What is the storage space consumed by the directory in bytes?

Answer: 6144

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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Q8. Consider a multi-processing system with two cores A and B with their own private caches and a single shared main memory using MESI cache coherence protocol. The following 4 lines of code are running in each of the two cores.
1. LW R1, M1
2. LW R2, M2
3. SW R3, M2
4. SW R2, M1

The addresses pointed by M1 and M2 map to different cache blocks. Consider the following execution sequence in the format; Core-Instruction Number. A-1, A-2, B-2, B-1, B-3, A-3, B-4, A-4. If the state of 4 blocks (M1 in A, M2 in A, M1 in B, M2 in B) can be represented as PQRS where P/Q/R/S can be any one of M/E/S/I. Accordingly, the initial state is IIII. Which one of the following represents the state of these blocks after the execution of these above 8 instruction sequences?
MMII
SSSS
MSIS
ISMI

Answer: MMII

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These are Multi-Core Computer Architecture Nptel Week 8 Answers

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