These are Multi-Core Computer Architecture Nptel Week 12 Answers
Q1. The number of cycles a packet can be delayed in the network without reducing application’s performance is known as _. Packet latency Network stall time Slack Critical time
Answer: Slack
Q2. Intel KNL has _ tiles in 2D mesh. 8 36 64 16
Answer: 36
These are Multi-Core Computer Architecture Nptel Week 12 Answers
Q3. Which one of the following emerging NoCs uses the concept of diverting light to a certain wavelength when voltage is applied? 3D NoC Nanophotonics RF waveguide wireless communication Vertical interconnect
Answer: Nanophotonics
Q4. Which one of the following is a 64-bit dual core VEGA processor? VEGA AS1061 VEGA AS2161 VEGA AS4161 VEGA AS1161
Answer: b. VEGA AS2161
These are Multi-Core Computer Architecture Nptel Week 12 Answers
Q5. Which one of the following statements is TRUE about layerwise DNN computation done on a TCMP system? Filter/weights are moved from global buffer to off-chip memory Output feature map is progressed from off-chip memory to global buffer Global buffer is directly connected to each PE using a dedicated bus Filter/weights are moved from off-chip memory to global buffer
Answer: Filter/weights are moved from off-chip memory to global buffer
Q6. Consider a 16 x16 Cmesh NoC structure in which each node is connected to 4 processing cores. The entire mesh structure is divided into 16 Wcubes. Each Wcube is marked with a 4 bit number. [Wcube- 0 (0000) to Wcube- 15 (1111)] Identify the correct Wcube to which Wcube-15 can be directly communicated? Wcube- 9 Wcube- 13 Wcube- 10 Wcube- 8
These are Multi-Core Computer Architecture Nptel Week 12 Answers
Q7. Consider a TCMP system with 64 tiles, where each tile consists of a superscalar processor, a private L1 cache and a shared distributed L2 cache. The total L2 cache on the chip is 16MB and L2 uses 64B blocks and is 8-way associative. Each L2 cache slice on-chip has all the 8 ways of the sets assigned to it. The L2 cache memory per tile division is such that total sets in L2 cache are uniformly partitioned across tiles in a sequential fashion. The system uses a 32-bit physical address. How many L2 cache sets are mapped per tile?
Answer: 512
These are Multi-Core Computer Architecture Nptel Week 12 Answers
Q8. Consider a TCMP system with a 4×4 mesh NoC where each tile consists of a superscalar processor, a private L1 cache and a shared distributed L2 cache. Let T0, T1, T2… ,T15 corresponds to the tiles where T0 is the bottom left tile and T15 the top right tile. Each tile has a 16KB 2-way associative L1 cache with a block size of 16B. The total L2 cache on the chip is 32MB and L2 uses 128B blocks and is 16-way associative. Each L2 cache bank has all the 16 ways of the sets assigned to it. The L2 cache memory per tile division is such that total sets in L2 cache are uniformly partitioned across all tiles in sequential fashion. The system uses a 40-bit physical address. T4 generated an L1 cache miss for the address A1=0x A8CD210652. As per L2 set mapping, tile Tx host the L2 set for A1. What is the value of x? (Hint: Possible value of x ranges from 0 to 15).
These are Multi-Core Computer Architecture Nptel Week 12 Answers
Q9. Consider a 4×4 NoC with CHIPPER routers. Preferred port is chosen by XY routing. Consider 4 packets that reach router 6 (routers are numberred from 0 to 15). The details of the packets (Packet number, Golden, Input Port, Destination) <P1, Yes, S, 10>, <P2, No, W, 14>, <P3, No, E, 9> and <P4, No, N, 6>. Tie between two non-golden flits are resolved using packet number. Higher the packet number, higher the priority. How many packets get productive output port in PDN?
Answer:
These are Multi-Core Computer Architecture Nptel Week 12 Answers
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