Multi-Core Computer Architecture | Week 2
Session: JULY-DEC 2023
Course Name: Multi-Core Computer Architecture
Course Links: Click Here
These are Multi-Core Computer Architecture Nptel Week 2 Answers
Q1. Which type of data hazard occurs when an instruction tries to read an operand before another instruction writes it?
RAW hazard
WAR hazard
WAW hazard
RAR hazard
Answer: RAW hazard
Q2. Which one of the following is true regarding pipelining in microprocessors?
Pipelining reduces the latency of a single instruction.
Pipelining improves the throughput of a program.
Pipelining increases the clock speed of the processor.
Pipelining reduces the execution time of an instruction.
Answer: Pipelining improves the throughput of a program.
These are Multi-Core Computer Architecture Nptel Week 2 Answers
Q3. Which type of hazard occurs when different instructions, at different stages in the pipeline, want to use the same hardware resource?
Data hazard
Control hazard
Structural hazard
Pipeline hazard
Answer: Structural hazard
Q4. Which one of the following is a characteristic feature of a typical RISC machine?
Complex instructions with longer execution time.
Memory-intensive instructions.
Load and store instructions.
Instructions with variable lengths.
Answer: Load and store instructions.
These are Multi-Core Computer Architecture Nptel Week 2 Answers
Q5. Which of the following statement is true with respect to an Instruction Fetch operation of a processor pipeline?
Contents from Instruction memory are transferred to ID/EX pipeline register
Contents from Instruction memory are transferred to IF/ID pipeline register
Contents from IF/ID pipeline register are transferred to ID/EX pipeline register
Contents from ID/EX pipeline register are transferred to IF/ID pipeline register
Answer: Contents from Instruction memory are transferred to IF/ID pipeline register
These are Multi-Core Computer Architecture Nptel Week 2 Answers
Q6. Consider 3 instructions I1, I2 and I3 given in the order of execution.
I1: ADD R1, R2, R3
I2: SUB R4, R1, R2
I3: XOR R2, R5, R3
The dependency between R2 of I1 and R2 of I3 is known as …………
input dependence
anti dependence
output dependence
true data dependence
Answer: anti dependence
These are Multi-Core Computer Architecture Nptel Week 2 Answers
Q7. The technique of separating dependent instruction from the source instruction by pipeline latency of the source instruction is called——–.
instruction folding
compiler scheduling
operand forwarding
bypassing
Answer: compiler scheduling
Q8. Assume an instruction pipeline with 5 stages namely IF, ID, EX, MEM and WB with individual latencies 50 ns, 30 ns, 70 ns, 85 ns, and 40 ns, respectively. Pipeline latch latency is10 ns. What is the pipeline cycle time in ns?
Answer: 95
Q9. Given a non-pipelined architecture running at 1.5GHz, that takes 5 cycles to finish an instruction. You want to make it pipelined with 5 stages. Due to hardware overhead, the pipelined design will operate only at 1GHz. 10% of memory instructions cause a stall of 30 cycles, 30% of branch instructions cause a stall of 2 cycles, and load-ALU combinations cause a stall of 1 cycle. Assume that in a given program, there exist 20% of branch instructions and 30% of memory instructions. 10% of instructions are load-ALU combinations. What is the speedup of the pipelined design over the non-pipelined design? Correct to 2 decimal places.
Answer: (Type: Range) 1.55,1.58
These are Multi-Core Computer Architecture Nptel Week 2 Answers
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