Multi-Core Computer Architecture | Week 7

Session: JULY-DEC 2023

Course Name: Multi-Core Computer Architecture

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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Q1. For a cache memory of given capacity, as block size increases, there is
an increase in compulsory misses and a decrease in conflict misses.
a decrease in compulsory misses and conflict misses.
an increase in compulsory misses and conflict misses.
a decrease in compulsory misses and increase in conflict misses.

Answer: a decrease in compulsory misses and increase in conflict misses.

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Q2. Which one of the following optimization reduces the cache miss penalty?
Pipelined caching
Multi-level caching
Way prediction
Multibanked caching

Answer: Multi-level caching

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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Q3. Which one of the following statements is FALSE?
Victim cache is added to a cache to hold recently evicted cache lines.
Early restart and critical word first techniques reduce miss penalty.
Harware prefetching reduces cache hit time.
Non-blocking cache results in increased cache bandwidth.

Answer: Harware prefetching reduces cache hit time.

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Q4. Which one of the following statements is TRUE?
Way prediction technique reduces miss penalty in caches.
The conflict miss rate is low in a direct-mapped cache compared to a set associative cache of similar cache configuration.
Direct-mapped caches can have associativity larger than one
Pipelined caches helps in faster clocking rate for cache.

Answer: Pipelined caches helps in faster clocking rate for cache.

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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Q5. The average memory access time for a memory hierarchy system with one level of cache and a main memory is 6 ns. The hit time and miss penalty of the cache is 2 ns and 100 ns, respectively. The hit rate of the cache (round off to two decimal places) is
0.94
0.96
0.02
0.04

Answer: 0.96

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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Q6. Assume an L1 cache with a hit rate of 85%, and an L2 cache with a local miss rate of 4%. If there are 1500 memory access initiated by CPU, then the number of memory access that will find a hit in L2 cache is _____.

Answer: 216

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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Q7. A cache has a hit time of 10 ns and hit rate of 60%. An optimization was made to increase hit rate to 70% but the hit time was increased to 15 ns. The optimization resulted in a 10% reduction in average memory access time. Assume that the miss penalty is unaffected by the optimization. The miss penalty of the cache (in ns) is _____.

Answer: 100

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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Q8. A 32-bit word processor is connected to a 16 KB, 4-way set-associative L1 cache having a block size of 32 B. Total physical address space is 256 MB. When an L1 cache miss occurs, it takes 25 cycles to fetch the first word of a block from L2 cache and 4 cycles for each subsequent word in the block. Assume that processor is stalled due to an L1 cache miss occurred on a word whose first byte address is 0x3416ACC. Assume that the word is a hit in L2 cache. How many cycles will the processor stall before it resumes execution if an early restart optimization done on L1 cache.?

Answer: 37

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These are Multi-Core Computer Architecture Nptel Week 7 Answers

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