# Multi-Core Computer Architecture | Week 3

Session: JULY-DEC 2023

Course Name: Multi-Core Computer Architecture

#### These are Multi-Core Computer Architecture Nptel Week 3 Answers

Q1. Which one of the following statements is/are TRUE?
I. A one-bit predictor changes the prediction value for each mis-prediction.
II. BPB stores the previous outcomes of the branch instruction.
III. (p,q) branch predictor uses the outcome of last p branches to index into the BPB where each entry has a q-bit predictor.
IV. If BTB can store one or more target instructions it can facilitate branch folding.

III only
I and II only
IV only
I, II, III and IV

Answer: I, II, III and IV

Q2. With respect to a MIPS multi-cycle floating point pipeline, which one of the following statements is FALSE?
RAW dependency stalls can happen even after enabling operand forwarding.
Even after operand forwarding, there will be 3 stalls between a pair of adjacent FADD instructions that has a RAW dependency between them.
Initiation Intervals of FMUL unit is 1 cycle.
Even after operand forwarding, there will be 7 stalls between a pair of adjacent FMUL instructions that has a RAW dependency between them.

Answer: Even after operand forwarding, there will be 3 stalls between a pair of adjacent FADD instructions that has a RAW dependency between them.

These are Multi-Core Computer Architecture Nptel Week 3 Answers

Q3. For filling the delay slot for a branch, an instruction is chosen from the target location of the branch if……….
the outcome of the branch is irrelevant
the probability of branch not taken is very high
the probability of branch taken and not taken is same
the probability of branch taken is very high

Answer: the probability of branch taken is very high

Q4. Branch Prediction Buffer with 64 rows is indexed by
outcome of last 16 branches
outcome of last 8 branches
lower order 6 bits of the address of the branch instruction
64 bits of the physical address of the branch instruction.

Answer: lower order 6 bits of the address of the branch instruction

These are Multi-Core Computer Architecture Nptel Week 3 Answers

Q5. Which of the following is best description of a (p, q) type branch predictor?
It uses the outcome of last p branches to index into the BPB where each entry has a q-bit predictor.
It uses the outcome of last 2p branches to index into the BPB where each entry has a q-bit predictor.
It uses the outcome of last p branches and last q bits of PC to index into the BPB to decide the predictor.
It uses the outcome of last q branches and last p bits of PC to index into the BPB to decide the predictor.

Answer: It uses the outcome of last p branches to index into the BPB where each entry has a q-bit predictor.

These are Multi-Core Computer Architecture Nptel Week 3 Answers

Q6. What is the latency of the floating-point Multiplier Unit in a MIPS processor?
7
6
4
1

These are Multi-Core Computer Architecture Nptel Week 3 Answers

Q7. Which one of the following branch handling approach allows a branch to take place after one instruction following the branch instruction?
Stall until branch direction is clear
Predict Branch Taken
Predict Branch Not Taken
Delayed Branch

Q8. Among the listed operations, which one is not having a fully pipelined implementation in a MIPS processor?
Floating Point Subtract
Floating Point Multiply
Floating Point Divide

These are Multi-Core Computer Architecture Nptel Week 3 Answers

Q9. Consider a (2,2) type branch predictor. BHT is indexed by the outcome of the last 2 branches. The BPB is initialized for NN/NT/TN/TT as 00/00/11/11 and is indexed with an NN entry in the first reference. Consider the last 6 actual outcomes of a single static branch, {oldest N N T T T N latest} where T means branch is taken and N means not taken. What will be the contents of BPB after the execution of the above mentioned 6 branch outcomes?
01/01/11/00
01/01/00/11
01/01/11/10
01/01/10/11