There are total __ steps for flip flop conversions 1 2 4 5
5
When toggle condition occurs in JK flip flop? J=1, K=1 J=0, K=0 J=1, K=0 J=0, K=1
J=1, K=1
The flip flop is a _ device. Unstable Bi-stable Both a and b None of the above
Bi-stable
How many inverters does the basic latch consists of? 1 2 3 4
2
The shift registers are categorized into ________types. 1 2 3 4
4
The flip flops works with __ Binary inputs Clock signal Both a and b None of the above
Both a and b
How many possible conversions are there to convert SR flip flop to other flip flops? 1 2 3 4
3
Practical
2.1
If A, B and C are the inputs of a full adder then the carry is given by __ A AND B OR (A OR B) AND C A OR B OR (A AND B) C (A AND B) OR (A AND B)C A XOR B XOR (A XOR B) AND C
A AND B OR (A OR B) AND C
How many AND, OR and EXOR gates are required for the configuration of full adder? 1, 2, 2 2, 1, 2 3, 1, 2 4, 0, 1
2, 1, 2
Half-adders have a major limitation in that they cannot __ Accept a carry bit from a present stage Accept a carry bit from a next stage Accept a carry bit from a previous stage Accept a carry bit from the following stages
Accept a carry bit from a previous stage
In parts of the processor, adders are used to calculate __ Addresses Table indices Increment and decrement operators All of the Mentioned
All of the Mentioned
In which operation carry is obtained? Subtraction Addition Multiplication Both addition and subtraction
Addition
The difference between half adder and full adder is __ Half adder has two inputs while full adder has four inputs Half adder has one output while full adder has two outputs Half adder has two inputs while full adder has three inputs All of the Mentioned
Half adder has two inputs while full adder has three inputs
2.2
Two input MUX have_________ select lines. 1 2 3 4
1
MUX is also known as Coder Parallel Adder Data Selector Gates
Data Selector
What is the expression for the sum(s) of a half adder if the inputs are A & B? S = A OR B S = A AND B S = A XNOR B S = A XOR B
S = A XOR B
While implementing NOT gate using 2:1 MUX, the two inputs will be_________ A=0 & B=1 A=1 & B=1 A=0 & B=0 A=1 & B=0
A=1 & B=0
To implement NOR gate using MUX, ___ 2:1 will be required. 2 3 4 5
2
If enable input is high then MUX is __– Enable Disable Saturation High Impedance
Disable
2.3
Which method of combination circuit implementation is widely adopted with maximum output functions and minimum requirement of ICs? Multiplexer Method Decoder Method Encoder Method Parity Generator Method
Decoder Method
Why are the lines specifically used for connecting two or more IC packages in accordance to its application in decoder circuit? It allows the reduction of digital function into similar function with more inputs & outputs It allows the expansion of digital function into similar function with more inputs & outputs It allows the reduction of digital function into different function with more inputs & outputs It allows the expansion of digital function into different function with more inputs & outputs
It allows the expansion of digital function into similar function with more inputs & outputs
Which of the following represents a number of output lines for a decoder with 4 input lines? 15 16 17 18
Decoders and Encoders are doing the reverse operation? True False
True
A decoder can be used as a demultiplexer by? tying all enable pins LOW tying all data-select lines LOW tying all data-select lines LOW using the input lines for data selection and an enable line for data input
using the input lines for data selection and an enable line for data input
The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with active-low outputs is 1110. As a result, output line 7 is driven LOW? True False
