VLSI Design Flow: RTL to GDS Nptel Week 5 Answers
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VLSI Design Flow RTL to GDS Nptel Week 5 Answers (July-Dec 2025)
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Question 1. We can build a Binary Decision Tree for a Boolean function using:
a) Fermat’s Last Theorem
b) Pythagoras Theorem
c) Quine’s Theorem
d) Shannon’s Expansion Theorem
These are VLSI Design Flow RTL to GDS Nptel Week 5 Answers
Question 2. Which of the following statements is/are true regarding simulation-based verification?
A. Design correctness can be proven using simulation-based verification for all non-trivial industrial designs.
B. Test vectors or stimuli are required for simulation-based verification.
C. The computational resources needed for simulation-based verification will typically increase with the number of test vectors or stimuli.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
Question 3. Which of the following statements is/are true?
A. If a Boolean function representation is canonical, two equivalent Boolean functions are represented identically.
B. ROBDD is a canonical representation of a Boolean function.
C. The size of an ROBDD for a Boolean function does not depend on the variable order.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
These are VLSI Design Flow RTL to GDS Nptel Week 5 Answers
Question 4. Among the following statements, which statement is correct about state minimization?
a) State minimization involves reducing the number of bits in the FSM’s representation by increasing the number of states.
b) State minimization involves deriving an FSM that has the minimum number of states and exhibits behavior totally different from the original FSM.
c) State minimization involves deriving an FSM that has the minimum number of states and exhibits the same behavior as the original FSM.
d) State minimization involves a transformation that allows an FSM to generate random outputs.
Question 5. To represent an FSM with nₛ states, how many bits are needed for one-hot encoding?
a) log₂(nₛ)
b) nₛ
c) (nₛ)²
d) nₛ + 1
These are VLSI Design Flow RTL to GDS Nptel Week 5 Answers
Question 6. Which of the following statements is/are true?
A. The circuit area of an FSM implementation always reduces if the number of states is increased
B. An FSM can be represented pictorially using a state diagram.
C. We often represent sequential circuits using an FSM in model checking
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
Question 7. Which of the following statements is/are correct?
A. Sum of Product (SOP) and Product of Sum (POS) are examples of two-level logic.
B. Two-level logic will typically have a greater number of logic gates between input and output compared to its equivalent multi-level logic.
C. Two-level logic is always more compact (having a smaller number of gates) than its equivalent multi-level logic.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
These are VLSI Design Flow RTL to GDS Nptel Week 5 Answers
Question 8. Match the following transformations done during multi-level logic optimization with their descriptions:
a) A-1, B-2, C-3, D-4
b) A-1, B-3, C-4, D-1
c) A-2, B-1, C-4, D-3
d) A-2, B-4, C-1, D-3
e) A-3, B-4, C-1, D-2
f) A-3, B-1, C-4, D-2
g) None of the above
Question 9. Which of the following files are typically given as input to Yosys for logic synthesis?
A. RTL code (such as top.v)
B. VCD file (such as top.vcd)
C. Library file in Liberty format (such as NangateOpenCellLibrarytypical.lib)
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
Question 10. Which of the following can be used for logic optimization of a digital circuit?
A. Controllability Don’t Cares
B. Satisfiability Don’t Cares
C. Observability Don’t Cares
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
These are VLSI Design Flow RTL to GDS Nptel Week 5 Answers