VLSI Design Flow: RTL to GDS Nptel Week 3 Answers
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VLSI Design Flow RTL to GDS Nptel Week 3 Answers (July-Dec 2025)
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Question 1. A code coverage tool is typically employed to measure and report the code coverage of the given:
a) SDC file.
b) RTL design
c) Timing report
d) Layout
These are VLSI Design Flow RTL to GDS Nptel Week 3 Answers
Question 2. Which coverage metrics report design features that have been exercised/not exercised in the given coverage model during simulation?
a) Code coverage
b) Functional Coverage
c) Branch coverage
d) Toggle coverage
Question 3. Which of the following statement(s) is/are true?
A. Functions in a Verilog code can only have delays modelled by posedge, but not by negedge
B. Functions in a Verilog code can call another function but not a task.
C. Tasks in a Verilog code can call another task but not a function.
D. Tasks in a Verilog code can have delays modelled by both posedge and negedge
a) Only A
b) Only B
c) Only C
d) Only D
e) Only A, B
f) Only A, C
g) Only A, B
h) Only B, C
i) Only B, D
j) Only C, D
Question 4. How can we specify connections for an instantiated module in a Verilog code?
A. By specifying connections in implicit order as declared in the instantiated module.
B. By specifying connections explicitly using the name of the ports of the instantiated module.
a) Only A
b) Only B
c) Both A and B
d) None of the above
Question 5. Which of the following are distinct features of the Hardware Description Languages (like Verilog) and are not present in C?
A. Integer data type
B. Concurrency
C. Notion of time
D. Electrical characteristics (such as driver strength)
a) Only A
b) Only B
c) Only C
d) Only D
e) Only A, B, C
f) Only A, B, D
g) Only A, C, D
h) Only B, C, D
Question 6. What is the internal representation of the integer 8’bz101?
a) 0000 z101
b) z101 z101
c) zzzz z101
d) z000 0101
Question 7. Assume a=3’b101, b=4’b0011, then what is the output of {a,b}?
a) 7’b1010011
b) 4’b0011
c) 4’b0111
d) 7’b0011101
These are VLSI Design Flow RTL to GDS Nptel Week 3 Answers
Question 8. The order of execution of various events in a given time slot in Verilog is governed by:
a) Race Event Queue
b) Stratified Event Queue
c) Coverage Event Queue
d) Circular Verification Queue at a given simulation time
Question 9. Which of the following are valid keywords in Verilog language?
A. begin
B. initial
C. always
D. mycomments
a) Only A, B, C
b) Only A, B, D
c) Only A, C, D
d) Only B, C, D
e) All of the above
Question 10. How can the default value of a parameter in a parameterized module be overridden for a given instantiation in Verilog?
a) It can be overridden by providing a non-default value outside all of the modules.
b) It can be overridden during instantiation by providing a non-default value using the keyword PARAMETER
c) It can be overridden during instantiation by providing non-default values within #().
d) It can never be overridden.
These are VLSI Design Flow RTL to GDS Nptel Week 3 Answers
