VLSI Design Flow: RTL to GDS Nptel Week 1 Answers
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VLSI Design Flow RTL to GDS Nptel Week 1 Answers (July-Dec 2025)
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Question 1. Which of the following statement(s) is/are correct regarding a die fabricated on a silicon wafer?
A. We perform photolithography for creating transistors on a die before slicing that die out from the wafer
B. We perform photolithography for creating transistors on a die after slicing that die out from the wafer
C. We create metallic connections between transistors on a die before slicing that die out from the wafer
D. We create metallic connections between transistors on a die after slicing that die out from the wafer
a) A, C
b) A, D
c) B, C
d) B, D
Question 2. Which of the following statements is true?
a) The Foundry provides layout of an integrated circuit to the Fabless design companies for fabrication
b) Foundry directly uses RTL obtained from fabless design companies for fabrication
c) Fabless design companies provide PDK to Foundries for fabrication
d) Nvidia is a fabless design company
These are VLSI Design Flow RTL to GDS Nptel Week 1 Answers
Question 3. Which statement best describes the features of FPGA-based design compared to standard cell-based design?
a) Lower design effort
b) Inferior PPA
c) Lower fixed cost
d) All of the above
Question 4. Among the following statements, which statement correctly describes the abstraction of RTL?
a) RTL contains an algorithm typically written in C++
b) RTL contains data flow descriptions typically written in Hardware Description Languages such as Verilog and VHDL
c) RTL contains transistor-level description typically written in SPICE
d) RTL contains a layout typically written in GDS format
These are VLSI Design Flow RTL to GDS Nptel Week 1 Answers
Question 5. Which among the following statement(s) is/are true?
A. We use the same mask for all the metal layers while performing photolithography for a typical integrated circuit.
B. Design description at a higher abstraction level contains more details than description at a lower abstraction level
C. Full custom design, cell-based design and FPGA-based design are a few examples of design styles.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only A, C
f) Only B, C
g) All of the above
h) None of the Above
Question 6. Which of the following statements is correct regarding Behavior Synthesis or High-level Synthesis?
a) It converts an un-timed algorithm written in high-level languages to a circuit containing resistors, capacitors, and metallic interconnects with appropriate parameters.
b) It converts an un-timed algorithm written in high-level languages to an RTL model.
c) It converts an un-timed algorithm written in high-level languages to a transistor-level SPICE netlist.
d) It converts an un-timed algorithm written in high-level languages to its corresponding layout.
These are VLSI Design Flow RTL to GDS Nptel Week 1 Answers
Question 7. Which of the following can be the cost metrics for behavioral synthesis?
a) Area
b) Latency
c) Power dissipation
d) All of the above
Question 8. What are the advantages of designing a chip at a higher level of abstraction, such as RTL, compared to directly making a layout at the transistor level?
A. Making changes and exploring trade-offs can take less time and computational effort in RTL.
B. Timing analysis is more accurate at the RTL compared to layout.
C. It is more accurate to compute parasitic capacitance at RTL since it contains all hardware details.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only A, C
f) Only B, C
These are VLSI Design Flow RTL to GDS Nptel Week 1 Answers
Question 9. Match the following:
A. Layout – i. Instantiating various pre-designed and pre-verified sub-systems or blocks in an SoC and making their connections
B. Standard cells – ii. Higher level of abstraction of a design consisting of functionality at the register transfer level
C. IP Assembly – iii. Final design representation in GDS format provided by the design team to a foundry for fabrication
D. RTL design – iv. Optimally designed logic gates (AND, OR, multiplexer, flip-flop, etc.) and made available in a library
a) A-iv, B-i, C-iii, D-ii
b) A-iii, B-i, C-ii, D-iv
c) A-iv, B-i, C-ii, D-iii
d) A-iii, B-iv, C-i, D-ii
Question 10. What is the advantage of employing behavioral synthesis in a design flow?
a) The generated RTL often lacks readability and debuggability.
b) It always increases the design effort for a chip.
c) It allows automatic exploration of different possible RTLs for the same algorithm.
d) All of the above
These are VLSI Design Flow RTL to GDS Nptel Week 1 Answers