VLSI Design Flow: RTL to GDS Nptel Week 4 Answers
Are you looking for VLSI Design Flow RTL to GDS Nptel Week 4 Answers ? All weeks solutions of this swayam course assignment are available here.
Table of Contents
VLSI Design Flow RTL to GDS Nptel Week 4 Answers (July-Dec 2025)
Course link: Click here to visit course on Nptel Website
Question 1. An initial block in a Verilog code has a blocking assignment with a delay specification of 2 ns. Typically, what will be the synthesis result of this assignment?
a) It will be synthesized into one latch
b) It will be synthesized into two latches
c) It will be synthesized into a flip-flop and a latch
d) It will be ignored by the synthesis tool
Question 2. A Boolean function y of three variables {x1,x2,x3} is as follows: y = x1′x2′x3′ + x1′x2x3′ + x1x2x3′ + x1x2x3. In the hypercube representation, which corners will have a value of 1 (the corners are represented as values of x1 x2 x3 in the following options)?
a) 000,010,110,111
b) 111,101,001,000
c) 000,101,001,111
d) 111,010,110,000
These are VLSI Design Flow RTL to GDS Nptel Week 4 Answers
Question 3. Which of the following statements is/are true regarding the Heuristic Minimizer designed for two-level logic minimization?
A. It is guaranteed to be the minimum.
B. It never terminates (ends).
C. It typically starts with an initial cover, and the solution is iteratively improved by applying some operators to it.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
Question 4. Consider the following statements about tools ICARUS, GTKWave, and COVERED used in simulation-based verification:
A. We can use the ICARUS tool to write a VCD file containing simulation results for a given Verilog design and testbench.
B. VCD files can never be used by GTKWave to show the simulation results.
C. COVERED tool is to measure the size covered by a given layout on the wafer.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
These are VLSI Design Flow RTL to GDS Nptel Week 4 Answers
Question 5. What is the prime motivation for “resource unsharing” while synthesizing an RTL code?
a) Reduce the area of a circuit
b) Reduce the delay of a long or critical path
c) Reduce the testability of a circuit
d) Reduce the reliability of a circuit
Question 6. Which of the following statements are examples of typical compiler optimizations used in RTL synthesis?
a) A dead code is made alive
b) An arithmetic operation is replaced by an equivalent, more costly arithmetic operation
c) An expression is replaced by a constant if possible
d) All of the above
These are VLSI Design Flow RTL to GDS Nptel Week 4 Answers
Question 7. Which of the following statements is/are correct?
A. While performing RTL synthesis of a Verilog ‘for loop’, the RTL synthesis tool typically does not need to know the number of iterations during compile time for proper synthesis.
B. The critical path before and after resource sharing always remains the same in RTL synthesis.
C. Functions in Verilog are always synthesized to a sequential logic block with one output (scalar or vector).
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
Question 8. What will be the typical result of RTL synthesis of the following Verilog code?
a) FSM
b) Multiplexer
c) Demultiplexer
d) Clocked Multiplexer
Question 9. While modeling a combinational circuit using an always block in a Verilog code, which of the following methods can avoid unintentional inference of latches?
a) Use the negedge of the clock rather than the posedge of the clock
b) Use a default statement to write to a variable and cover all the possible paths in a “case statement”
c) Use an initial block inside the always block
d) Use wire instead of reg for a variable
These are VLSI Design Flow RTL to GDS Nptel Week 4 Answers
Question 10. Which of the following statements is/are true regarding RTL synthesis?
A. During parsing, typically, a hierarchical data structure called a parse tree or syntax tree is built.
B. During elaboration, modules with distinct interfaces can be created for each distinct set of parameters used during instantiation.
C. Some Verilog constructs, such as fork-join, force-release, can be ignored by an RTL synthesis tool.
a) Only A
b) Only B
c) Only C
d) Only A, B
e) Only B, C
f) Only A, C
g) All of the above
h) None of the above
These are VLSI Design Flow RTL to GDS Nptel Week 4 Answers
