VLSI Design Flow: RTL to GDS Nptel Week 2 Answers
Are you looking for VLSI Design Flow RTL to GDS Nptel Week 2 Answers ? All weeks solutions of this swayam course assignment are available here.
Table of Contents
VLSI Design Flow RTL to GDS Nptel Week 2 Answers (July-Dec 2025)
Course link: Click here to visit course on Nptel Website
Question 1. Arrange the following tasks involved in a typical process to create a mask for photolithography in their order of execution (first to last):
A. Etching is performed on the Chromium layer to get the required pattern
B. A protective layer called a Pellicle is added on to the mask.
C. Complex features of the given layout are converted to simpler shapes for mask writing.
D. The features written on the mask are inspected for any defects.
a) C-D-B-A
b) D-C-B-A
c) A-D-C-B
d) C-A-D-B
Question 2. Which of the following statement(s) is/are true regarding the packaging/packages of a chip?
A. After packaging a die in a supporting case, it is directly shipped to the market without any further testing.
B. Packages do not impact the timing behavior of a chip.
C. Packages can impact the heat drawn from a die using heat sinks.
D. Packages prevent any mechanical damage and corrosion on the chip.
a) Only A
b) Only B
c) Only C
d) Only D
e) Only A, B
f) Only B, C
g) Only C, D
h) Only B, D
i) Only A, B, C
j) Only B, C, D
k) All of the above
l) None of the above
These are VLSI Design Flow RTL to GDS Nptel Week 2 Answers
Question 3. Suppose a foundry fabricates a die with a yield of 80%. The foundry wants to deliver one million good dies to a customer. On a single wafer, 400 dies are produced. How many wafers does the foundry need to process to make the above delivery to the customer?
a) 3125
b) 4125
c) 5125
d) 6125
Question 4. Simulation techniques ensure the functional correctness of an RTL using:
a) Test stimuli or Test patterns
b) Formal Methods
c) Deductions
d) Property Checking
These are VLSI Design Flow RTL to GDS Nptel Week 2 Answers
Question 5. Arrange the following tasks of physical design in the sequence of execution (first to last).
A. Placement
B. Routing
C. Clock Tree Synthesis
D. Floorplanning
a) D-B-C-A
b) C-B-D-A
c) B-D-C-A
d) D-A-C-B
Question 6. How can defects manifest themselves in an integrated circuit?
a) Short-circuit
b) Open-circuit
c) Change in gate delay
d) All of the above
These are VLSI Design Flow RTL to GDS Nptel Week 2 Answers
Question 7. Which of the following inputs are typically given to a physical design tool for creating its layout?
A. Expected timing behavior (such as clock frequency)
B. Functionality of the design in the form of RTL design
C. Abstract physical information of standard cells (physical library)
D. Size and shape of the die
a) Only A, B
b) Only A, C
c) Only A, D
d) Only B, C
e) Only B, D
f) Only C, D
g) Only A, B, C
h) Only A, B, D
i) Only A, C, D
j) Only B, C, D
Question 8. Which of the following statement(s) is/are true?
A. Netlist generated by a logic synthesis tool majorly contains instances of standard cells and their connections.
B. Ports of a design in a netlist are used to communicate with the external world.
C. A netlist cannot contain multiple instances of the same standard cell with different instance names.
D. RTL design, libraries in Liberty format, and constraints in SDC format are typically given as inputs to a logic synthesis tool.
a) Only A, B
b) Only A, C
c) Only A, D
d) Only B, C
e) Only B, D
f) Only C, D
g) Only A, B, C
h) Only A, B, D
i) Only A, C, D
j) Only B, C, D
These are VLSI Design Flow RTL to GDS Nptel Week 2 Answers
Question 9. Match the following:
A. Routing → i. Planning and deciding how the clock signal reaches each clocked element.
B. Chip Planning → ii. Creates connections for the nets
C. Clock Tree Synthesis → iii. Regions on the layout are allocated for standard cells and macros.
a) A-iii, B-i, C-ii
b) A-iii, B-ii, C-i
c) A-ii, B-iii, C-i
d) A-ii, B-i, C-iii
Question 10. Which task converts a netlist defined in terms of generic gates to a netlist defined in terms of standard cells?
a) Hardware-software Partitioning
b) Behavior Synthesis
c) Routing
d) Technology Mapping
These are VLSI Design Flow RTL to GDS Nptel Week 2 Answers
