Digital Circuits Week 9 Nptel Assignment Answers

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Digital Circuits Week 9 Nptel Assignment Answers
Digital Circuits Week 9 Nptel Assignment Answers

Digital Circuits Week 9 Nptel Assignment Answers (July-Dec 2024)


Q1.‘‘Which of the following statement is TRUE?
a) In arandom-access memory. the access time depends on the location of the word.
b) In a random-access memory. the access time is independent of the location of the word.
c) Ina sequential access memory. the access time is independent of the location of the word.
d) Access time is same for a location in both the random- and the sequential-access memories.

Answer: b) In a random-access memory. the access time is independent of the location of the word.


Q2. A memory unit ©1024 X 64” is specified by the number of words times the number of bits per word. How many address lines are needed for the given memory unit?

A)8

B) 9

C) 10

D) 11

Answer: C) 10


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Q3‘What memory address range is NOT represented by chip #1 and chip #2 in the figure. A0 to A15 in the figure are the address lines and CS means chip select.
a) 0100-02FF
b) 1500-16FF
c) FO00-FAFF
d) F800-FOFF

Answer: b) 1500-16FF


Q4 The minimum number of transistors required to make a dynamic RAM cell is? 
a) 1 
b) 2 
c) 3
d) 4

Answer:a) 1 


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Q5.‘For the given circuit. identify the outputs A and B. (the ‘x indicates a connection) 

a) A=XY’ +XZ’ and B=XZ’+XY’ +YZ
b) A=XY+XZ’ and B=XZ’+XY’ +YZ
c) A=Y’Z+XZ’ and B=XZ’+XY’ +Y’Z
d) A=X’Y’+XZ’ and B=XZ’+XY’ +YZ

Answer: a) A=XY’ +XZ’ and B=XZ’+XY’ +YZ


Q6.Which of the following statements is FALSE?
A) SRAM memories has shorter READ and WRITE cycles compared to DRAM
B) DRAM memories has longer READ and WRITE cycles compared to SRAM
C) SRAM memories occupies minimal area compared to DRAM memories
D) SRAM memories occupies larger area compared to DRAM memories

Answer : C) SRAM memories occupies minimal area compared to DRAM memories


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Q7.‘What is the ROM size when it has 16-bit address lines as input and 8-bit data lines as output?
‘What is the ROM size when it has 16-bit address lines as input and 8-bit data lines as output?
A) 2^16 x 8 bits 
B) 2^8x 16 bits 
C) 16^2 x 8 bits 
D) 2^15 x 8 bits 

Answer: A) 2^16 x 8 bits 


Q8. Which of the following statements is TRUE? 
A) Hamming code can correct and detect only single bit errors
B) Hamming code can correct and detect up to two bit errors
C) Hamming code can correct and detect up to three bit errors
D) Hamming code can correct and detect up to four bit errors

Answer: A) Hamming code can correct and detect only single bit errors


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Q9.‘Which of the following technique is used to erase the data in EEPROM memory?
a) By heating the memory chip
b) Exposing to ultra-violet light
c) By applying an electrical signal
d) None of the above

Answer: c) By applying an electrical signal


Q10.A 12-bit hamming code read from a memory location. This hamming code contains 8-bit data and 4-bit code word. What was the original 8-bit data word stored in the memory location if the 12-bit hamming code is (0011 1011 1110)?

A) (1001 1110)2

B) (1101 1110)2

C) (1101 1101)2

D) (0010 1101)2

Answer: B) (1101 1110)2


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Q11.In hamming code,how many check bits are required for a data word of 25 bits?
a) 4
b) 5
c) 6
d)7

Answer :c) 6


Q12.Find the 12-bit hamming code for the given 8-bit data (1100 0011)2
A) (1101 1000 1100)2
B) (1010 1000 0011)2
C) (01010111 1100)2
D) (0010 0111 0011)2

Answer: B) (1010 1000 0011)2


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Q13.‘Which of the following statement is TRUE?
a) PAL has fixed AND array and fixed OR array
b) PAL has programmable AND array and fixed OR array.
c) PLA has fixed AND array and fixed OR array
d) PLA has programmable AND array and fixed OR array

Answer: b) PAL has programmable AND array and fixed OR array.


Q14.CPLD stands for . 
a) Combined programmable logic device 
b) Complex programmable logic device
c) Complement programmable logic device 
d) Complex permanent logic device 

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Answer: b) Complex programmable logic device


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These are Digital Circuits Week 9 Nptel Assignment Answers


Q15.Identify the functions (F1 F2 F3) implemented by following PLA circuit? 

A) F1=ABC F2,=C’B’ F3=A’B’C+B’C’

B) F1= ABC+B’C’ F2=ABC F3=A’BC’+B’C’
C) F1= A’BC+B’C’ F2,=ABC F3;=A’BC’+B’C’
D) F1= ABC+B’C’ F2=ABC’ F3=A’BC+B’C’

Answer:  B) F1= ABC+B’C’ F2=ABC F3=A’BC’+B’C’


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These are Digital Circuits Week 9 Nptel Assignment Answers

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