Q5.‘‘What is the output (QxQsQcQo) sequence of the following circuit after 5 clock transitions? (Assume initial output state of the all FFs are logic ‘0’.
A) 0001 B) 1000 C)1110 D)0110
Answer: C)1110
Q6.‘Which of the state diagram represents the following circuit?
Q7. A finite state machine (FSM) is implemented using the D flip-flops A and B. and logic gates, as shown in the figure below.
Assume that Xp is held at logic ‘1° throughout the operation of the FSM. When the FSM initialized to the state QaQp=00 and clocked, after two clock cycles, what will the output? A) 00 B) 11 0) 10 D) 01
Q13.Which of the following is not an application of a shift register circuit? A) Serial to parallel converter B) Sequence generator C) Look ahead carry adder D) Delay unit
Answer:C) Look ahead carry adder
Q14.A counter is constructed with three D flip-flops. The input-output pairs are named (Do. Qo). (D1. Q1). (D2. Q2). where the subscripts 0 denotes the least significant bit. The output sequence is desired to be the grey code sequence 000, 001, 011, 010, 110, 111, 101, and 100 repeating periodically. Note that the bits are listed in the Q2Q1Qo format. The combinational logic expression for Dr is.
