# Digital Circuits Week 4 Nptel Assignment Answers

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## Table of Contents

** Digital Circuits Week 4 Nptel Assignment Answers (July-Dec 2024)**

**Q1.**Which of the following property is WRONG?

A) A XOR 0 = A’

B) A XOR 1 = A’

C) A XOR A = 0

D) A XOR A’ = 1

**Answer: A) A XOR 0 = A’**

**Q2. **Minimum number of NAND gates are required to design a 2-input XOR gate is

A) 3

B) 4

C) 5

D) 6

**Answer: B) 4**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q3.**Which of the following logic function is implemented by the circuit given below?

A) NAND

B) NOR

C) XOR

D) XNOR

**Answer: A) NAND**

**Q4** How many transistors are required to design a CMOS 2-input NOR gate?

A) 2 PMOS and 1 NMOS transistors

B) 1 PMOS and 2 NMOS transistors

C) 3 PMOS transistors

D) 2 PMOS and 2 NMOS transistors

**Answer: **D) 2 PMOS and 2 NMOS transistors

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q5.**What is a hazard in digital circuits?

A) An error in the physical layout of the circuit

B) A temporary fluctuation in output due to changes in input

C) A permanent fault in the circuit

D) A delay in the clock signal

**Answer: B) A temporary fluctuation in output due to changes in input**

**Q6** In digital circuits, what type of hazard occurs when a single input change causes multiple changes in output before settling?

A) Static-1 hazard

B) Static-0 hazard

C) Dynamic hazard

D) Glitch hazard

**Answer :C) Dynamic hazard**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q7. **A static-0 hazard in a digital circuit occurs when:

A) The output should remain 0, but temporarily goes to 1

B) The output should remain 1, but temporarily goes to 0

C) The output oscillates between 0 and 1

D) The output remains at a constant 0

**Answer: A) The output should remain 0, but temporarily goes to 1**

**Q8. **Which of the following options correctly represents the SUM and CARRY outputs for a half adder?

A) SUM = A XOR B, CARRY = A.B

B) SUM = A XNOR B, CARRY = A.B

C) SUM = A XOR B, CARRY = A+B

D) SUMA.B, CARRY = A XOR B

**Answer: A) SUM = A XOR B, CARRY = A.B**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q9. **What is the primary difference between a half adder and a full adder?

A) A half adder can add two bits while a full adder can add three bits including the carry.

B) A half adder can subtract two bits while a full adder can add two bits.

C) A half adder can add three bits while a full adder can add two bits including the carry.

D) A half adder can multiply two bits while a full adder can add two bits.

**Answer:A) A half adder can add two bits while a full adder can add three bits including the carry.**

**Q10.**How many half adders are required to construct a full adder?

A) 1

B) 2

C) 3

D) 4

**Answer:B) 2**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q11.**When the set of input data to an even parity generator is 01111, the output will be

A) 1

B) 0

C) Don’t care

D) Depends on the previous input

**Answer : B) 0**

**Q12.Consider the circuit shown below. Which of the following statements correctly describe the output X?**

A) X is the generated carry-out bit

B) X is equal to logic 1 when addition is performed and X is equal to logic 0 whensubtraction is done.

C) X is equal to logic 1 if there is an overflow during either addition or subtraction.

D) X is equal to logic 0 if there is an overflow during either addition or subtraction.

**Answer: B) X is equal to logic 1 when addition is performed and X is equal to logic 0 whensubtraction is done.**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q13. **The product term to be included to remove possible static hazard for the function f(Y,W,X)=WX + W’Y’ is

A) WY’

B) XY’

C) W’X’

D) XY

**Answer:B) XY’**

**Q14. **Which of the following statement if FALSE?

A) Parity checking circuits are used for error dectection and correction

B) Parity generator circuit generates the parity bit before transmitting.

C) Parity checker circuits checks the parity at the reciever

D) Even parity checker output logic 1 when input contains even number of logic 1s

**Answer: D) Even parity checker output logic 1 when input contains even number of logic 1s**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

**Q15.**How many minimum number of transistors required to design a CMOS inverter?

A) 1 PMOS and 1 NMOS

B) 2 PMOS and 1 NMOS

C) 2 NMOS

D) 2 PMOS

**Answer: A) 1 PMOS and 1 NMOS**

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**These are Digital Circuits Week 4 Nptel Assignment Answers**

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