Hardware Modeling using Verilog Nptel Week 4 Answers
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Hardware Modeling using Verilog Nptel Week 4 Answers (July-Dec 2025)
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Question 1. For the statement “A = B + C” inside a procedural block, which of the following alternatives are valid?
a) A is a reg type variable, B & C are wire type variables.
b) A & B are reg type variables, C is a wire type variable.
c) A is a wire type variable, B & C are reg type variables.
d) A, B and C are all wire type variables.
Question 2. For the following code segment, the final value of variable “c” will be
integer a, b, c;
initial
begin
b = 2 ; c = 15 a = 20
a = b * c;
b = a - 12
C = a + b;
end
Question 3. For the following code segment, the final value of variable “c” will be
integer a, b, c;
initial
begin
a = 20 b = 2 c = 15
end
initial
begin
a <= #5 b * c;
b <= #5 a -12;
c <= #5 a + b;
end
Question 4. What will the following code segment do?
always (posedge clock)
begin
X = z;
Y = z;
Z = x;
end
a) Shift the values stored in the three variables.
b) All the variables will get the value previously stored in “x”.
c) All the variables will get the value previously stored in “y”.
d) All the variables will get the value previously stored in “z”.
These are Hardware Modeling using Verilog Nptel Week 4 Answers
Question 5. If the 5-bit variable “data” declared as reg [4:0] data is initialized to 5’b01101, what will be its value after execution of the following code segment?
always (posedge clock)
begin
data [4:0] = data [4:0] >> 2;
end
a) 5’b00110
b) 5’b00011
c) 5’b10100
d) None of these.
Question 6. What will the following code segment generate on synthesis?
always (posedge clock)
begin
y = x;
z = y;
end
a) Two D flip-flops all fed with the data “x”.
b) A 2-bit shift register.
c) A 2-bit parallel-in parallel-out register.
d) None of these.
Question 7. What will the following code segment generate on synthesis?
always (posedge clock)
begin
y <= x;
z <= y;
w <= z;
end
a) A 3-bit parallel-in parallel-out register.
b) Three D flip-flops all fed with the same input “z”.
c) A 3-bit shift register.
d) None of these.
These are Hardware Modeling using Verilog Nptel Week 4 Answers
Question 8. What function does the following Verilog module realize in the final output “f”?
module mystery (f, a, b, c);
input a, b, c;
output f;
wire t;
xor G1 (t, a, b);
xor G2 (f, t, c);
endmodule
a) The carry function of a full adder with inputs “a”, “b”, “c”.
b) The sum function of a full adder with inputs “a”, “b”, “c”.
c) 3-variable majority function with inputs “a”, “b”, “c”.
d) None of these.
Question 9. Which of the following is/are true for “generate” blocks in Verilog?
a) Multiple copies of code blocks are generated dynamically before simulation or synthesis.
b) Can be used to instantiate multiple copies of some module.
c) Cannot be used along with a variable of type “genvar”.
d) None of these.
Question 10. Which of the following is/are not true for user defined primitives in Verilog?
a) Can be used to specify a combinational circuit with any number of outputs.
b) Can be used to specify a combinational circuit with a single output.
c) Can be used to specify a finite state machine with one or two state variables.
d) Can be used to specify a finite state machine with only one state variable.
These are Hardware Modeling using Verilog Nptel Week 4 Answers
