Hardware Modeling using Verilog Nptel Week 3 Answers
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Hardware Modeling using Verilog Nptel Week 3 Answers (July-Dec 2025)
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Question 1. Which of the following statements is/are true for the “assign” statement in Verilog?
a) It implements continuous assignment of the expression specified on the right-hand side to a “net” type variable specified on the left-hand side.
b) It implements continuous assignment of the expression specified on the right-hand side to a “reg” type variable specified on the left-hand side.
c) It can be used to assign values to a “reg” type variable in synchronism with a clock.
d) None of these.
Question 2. Which of the following are true for the following code segment?
nginxCopyEditinput [3:0] a;
input [3:0] b;
input sel;
output [3:0] f;
assign f = sel? a: b;
a) One 4-to-1 multiplexer will be generated.
b) Four 2-to-1 multiplexers will be generated.
c) One 4-to-1 and one 2-to-1 multiplexers will be generated.
d) None of these.
Question 3. Which of the following constructs will be generating a demultiplexer, where “a”, “b” and “c” are variables?
a) assign a = b[c];
b) assign b[c] = a;
c) assign a = b[c] & ~b[~c];
d) assign a = b & ~c
These are Hardware Modeling using Verilog Nptel Week 3 Answers
Question 4. What does the following code segment implement?
javaCopyEditassign ql = ~(q2| y);
assign q2 = ~(x | ql);
a) A 1-bit flip-flop with clocked input.
b) A 2-bit right-shift register.
c) Two NOR gates connected in cascade.
d) A 2-bit comparator.
e) None of these.
Question 5. Which of the following is/are true for the “initial” procedural block in Verilog test benches?
a) It specifies a procedural block that is executed repeatedly.
b) It specifies a procedural block that can be used for synthesis.
c) It specifies a procedural block that is executed only once.
d) None of these.
Question 6. What will be the time period of the repetitive signal “stim” generated by the following code segment?
csharpCopyEditinitial stim = 1'b0;
always #37 stim = ~stim;
a) 0
b) 7
c) 14
d) None of these.
These are Hardware Modeling using Verilog Nptel Week 3 Answers
Question 7. Which of the following event expressions can be used to specify a procedural block that will execute whenever there is a change in the state of the signal “clk”?
a) always @(posedge clk)
b) always @(negedge clk)
c) always @( c| k = 0 or clk=1)
d) always @(clk)
e) None of these.
Question 8. Which of the following is true for the following module?
matlabCopyEditmodule guess (a, b);
input [1:0] b;
output reg a;
always (b)
begin
if (b == 2'b00) a = 1'b1;
else if (b == 2'b11) a = 1'b1;
else a = 1'b0;
end
endmodule
a) A combinational circuit implementing a XOR function will be generated.
b) A combinational circuit implementing an AND function will be generated.
c) A latch will be generated for the output “a”.
d) None of these.
These are Hardware Modeling using Verilog Nptel Week 3 Answers
Question 9. In which of the following case(s), the synthesis tool will infer a sequential circuit from the description of an always block?
a) Every branch of a conditional statement defines all the outputs.
b) Every branch of a case statement defines all outputs.
c) Some branches of a case statement do not have defined outputs.
d) Some branches of conditional statements do not have defined outputs.
e) None of these.
These are Hardware Modeling using Verilog Nptel Week 3 Answers
Question 10. Consider the following code segment:
rubyCopyEditreg [0:7] a, b, c, d;
initial begin
#4 a = 10 b = 8 ; c = 2 ; d = 15 ;
#4 a = 4 b a; c = b; d = c; =
end
What will be the values of variables a, b, c and d after time interval of 10 unit?
a) a = 10 b = 8 c = 2 and d = 15
b) a = 4 b = 8 c = 2 and d = 15
c) a = 4 b = 4 c = 4 and d = 4
d) None of these.
Question 11. Given the following Verilog code:
vbnetCopyEditreg clk;
integer y;
initial clk = 1'b0;
always #5 clk = ~clk;
initial
begin
y = 2435
while (y >= 45) %35 y = y >> 1;
end
The while loop will be iterated number of times.
Question 12. Given the following Verilog code:
pgsqlCopyEditinteger x, y;
reg clk;
always #5 clk = ~clk;
initial
begin
#5 clk = 1'b0; x = 0
#3 y = 12
end
initial
begin
#5 y = 7
repeat (y)
#5 x = x + y;
end
The final value of X will be.
These are Hardware Modeling using Verilog Nptel Week 3 Answers