Hardware Modeling using Verilog Nptel Week 1 Answers
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Hardware Modeling using Verilog Nptel Week 1 Answers (July-Dec 2025)
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Question 1. Which of the following VLSI design styles only allows layouts of functional blocks with fixed height?
a) Standard cell
b) Full custom
c) FPGA
d) None of these
Question 2. Which of the following statement(s) is/are false?
a) FPGA based design is slower than standard cell based design.
b) Standard cell based design is faster than full custom design.
c) FPGA based design is faster than full custom design.
d) None of these
Question 3. Which of the following design descriptions represent a netlist?
a) A set of gates and their interconnections
b) Interconnection of register transfer level components
c) The truth table representation of a function
d) All of these
Question 4. Which of the following is carried out before the others in a typical VLSI design flow?
a) Logic design
b) Data path design
c) Physical design
d) Layout design
Question 5. What are the basic building blocks in a switch level description of a VLSI design?
a) Gates
b) RTL level modules
c) Transistors
d) Relay switches
Question 6. Which of the following is used to specify a design in Verilog?
a) A Verilog module
b) A Verilog test bench
c) A Verilog design bench
d) None of these
Question 7. The process of converting a function specification to a netlist of gates/modules is called:
a) Evolution
b) Simulation
c) Synthesis
d) Emulation
Question 8. For FPGA design style, what is the full form of CLB?
a) Combinational logic block
b) Constant logic bit
c) Cumulative logic bias
d) Combinational latch block
Question 9. The truth table description of a function represents a behavioral description.
a) True
b) False
Question 10. How many distinct functions of 3 variables are possible?
a) 8
b) 256
c) 9
d) None of these
These are Hardware Modeling using Verilog Nptel Week 1 Answers
