Hardware Modeling using Verilog Nptel Week 2 Answers
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Hardware Modeling using Verilog Nptel Week 2 Answers (July-Dec 2025)
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Question 1. A Verilog module can describe a hardware component at which level of abstraction?
a) Behavioral level
b) Netlist of gates
c) Netlist of other Verilog modules
d) All of these
Question 2. Given the Verilog code, which of the following statement(s) is/are true?
module fun (f, a, b, c);
input a, b, c;
output f;
wire f, t1, t2;
assign ti = a ^ b;
assign t2 = b A c;
A t2; assign f = t1
endmodule
a) It represents structural description of the Boolean function f = a xor c.
b) It represents behavioral description of the Boolean function f = a and b.
c) It represents behavioral description of the Boolean function f = a or b.
d) None of these.
Question 3. Which of the following statement(s) is/are true for the “assign” statement?
a) A register type variable can be assigned a value.
b) A net type variable can be assigned a value.
c) No value can be assigned.
d) None of these.
These are Hardware Modeling using Verilog Nptel Week 2 Answers
Question 4. Given the Verilog code segment:
input a, b, c, d;
output f;
wire f1, f2;
assign f1 = a & c;
assign f2 = ~(f1 | b);
What will be the values of f1 and f2 if a = 0, b = 1, c = 1, and d = 0?
a) f1 = 0 , f2 = 0
b) f1 = 0 , f2 = 1
c) f1 = 1 , f2 = 0
d) f1 = 1 , f2 = 1
Question 5. Which of the following statement(s) is/are true regarding the Verilog module shown below?
module fun3 (f, a, b, clk);
input [7:0] a, b;
input clk;
output f;
integer f;
always @(negedge clk)
begin
f = a + b;
end
endmodule
a) The size of f will be inferred as 8 bits
b) The size of f cannot be inferred
c) The size of f will be inferred as 9 bits
d) None of these
These are Hardware Modeling using Verilog Nptel Week 2 Answers
Question 6. Consider the Verilog code presented below:
reg [0:3] data1;
reg [0:3] data2;
reg [0:3] res;
res = data1 ^ data2;
What will be the value of “res” after simulating the code with the initialization data1 = 4’b0011 and data2 = 4’b0110?
a) 4’b0111
b) 4’b0011
c) 4’b0001
d) None of these
Question 7. Consider the Verilog code for declaring a multi-dimensional array:
reg [10:0] data [0:7];
Which of the following assignment statement(s) is/are correct?
a) data[0] = 8’b11111111;
b) data[0] = 11’b0;
c) data[0] = 1’b1;
d) All of these
Question 8. Which of the following statement(s) is/are true about defining constant in Verilog?
a) The statement parameter defines a constant of size 4-bit. H = 25
b) The statement parameter H = 36 defines a constant of size 32-bit.
c) The statement parameter H = 4’b1011; defines a constant of size 4-bit.
d) None of these.
Question 9. Which of the following logic expressions are correct? Assume that variable b is a 1-bit wire and z and x denote high impedance state and unknown logic state.
a) b & x = x
b) b | x = x
c) b ^ x = x
d) All of the above
Question 10. Consider the following Verilog code:
b = {2’b01, {2{2’b00}}, 2’b10};
The value assigned to b will be (in decimal). Assume that b is an 8-bit reg type variable.
These are Hardware Modeling using Verilog Nptel Week 2 Answers
