Computer Architecture and Organization Week 5 Answers Nptel
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Computer Architecture and Organization Week 5 Answers (July-Dec 2025)
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Question 1. How many minimum external connections are required for a 4096 x 16-bit memory chip?
a) 45
b) 47
c) 32
d) 48
Question 2. In a DRAM design, how many transistors and how many capacitors are required to implement a 1, 64-bit word (i.e., 64 storage cells)?
a) 32 transistors and 32 capacitors
b) 64 transistors and 64 capacitors
c) 128 transistors and 128 capacitors
d) 64 transistors and 128 capacitors
Question 3. Which of the statements below is/are true?
a) SRAM does not require refresh circuitry, whereas DRAM requires periodic refresh.
b) For the same capacity and word width, DRAM has larger cell area per bit than SRAM.
c) Cache memories are typically built using SRAM, while main memory uses DRAM.
d) The access time of SRAM is higher than that of DRAM.
e) In DRAM, address lines are often multiplexed into row and column parts, driven by RAS’ and CAS’.
Question 4. Consider a 2 Mbit memory organized as 2048 (rows) and 128 (columns). If the data bus is 8-bit wide, the total number of address lines required will be:
a) 18
b) 14
c) 15
d) 20
Question 5. For a DDR memory module with a bus clock of 400 MHz and a 128-bit wide data path, what is the maximum data transfer rate?
a) 6.4 GB/s
b) 25.6 GB/s
c) 12.8 GB/s
d) 3.2 GB/s
These are Computer Architecture and Organization Week 5 Answers Nptel
Question 6. You have 4 KByte memory chips. How many such chips are required to build a 32 KByte memory system? Assume the processor data lines are 8-bits wide (byte-oriented). What will be the address range for selecting the 3rd memory chip, assuming the first chip is numbered 0?
a) 8, 1800H to 1FFFH
b) 8, 2000H to 27FFH
c) 8, 1000H to 1FFFH
d) 8, 2000H to 2FFFH
Question 7. Consider a memory system that takes 15 nanoseconds to service the access of a single 32-bit word. What will be the maximum data transfer rate?
a) 2133.33 Mbits per second
b) 4266.67 Mbits per second
c) 266.67 Mbits per second
d) 1066.67 Mbits per second
Question 8. Four 8 MByte memory chips (named M0, M1, M2, M3) are connected together to form an interleaved byte-addressable memory system. The processor is byte-oriented. Which memory modules will the addresses 00ABC3E1H and 00F4CDE2H map to?
a) M1 and M2
b) M0 and M2
c) M1 and M3
d) M1 and M4
e) M3 and M4
These are Computer Architecture and Organization Week 5 Answers Nptel
Question 9. Which of the following is/are true?
a) Single Data Rate (SDR) SDRAM transfers two words per clock cycle.
b) Double Data Rate (DDR) SDRAM transfers data on both the rising and falling edges of the clock.
c) A Dual In-line Memory Module (DIMM) is made up of multiple DRAM ICs mounted on a PCB.
d) A SO-DIMM is electrically incompatible with a regular DIMM (they are always different in signaling, not only form factor).
e) SDRAM devices often use an internal column counter to support burst transfers without external CAS pulses.
Question 10. In SDRAM, what does “burst mode” operation refer to?
a) Accessing multiple consecutive columns from the same row with a single column address input.
b) Using multiple DRAM chips in parallel to widen the data bus.
c) Refreshing all rows in a short burst at startup.
d) Switching between SDR and DDR modes dynamically.
These are Computer Architecture and Organization Week 5 Answers Nptel