Computer Architecture and Organization Week 1 Answers Nptel
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Computer Architecture and Organization Week 1 Answers (July-Dec 2025)
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Question 1. Which component of the processor holds the address of the memory location to be accessed?
a) Memory Data Register (MDR)
b) Instruction Register (IR)
c) Memory Address Register (MAR)
d) Program Counter (PC)
Question 2. Match the generation of computer systems with the correct technologies:
I. First Generation → a) LSI and VLSI circuits
II. Second Generation → b) Vacuum tubes and relays
III. Third Generation → c) Transistors
IV. Fourth Generation → d) SSI and MSI circuits
a) I-b, II-c, III-d, IV-a
b) I-b, II-c, III-a, IV-d
c) I-a, II-b, III-c, IV-d
d) I-d, II-a, III-b, IV-—
Question 3. Consider a 32-bit machine where an instruction SUB R3, VAR (R3 = R3 — Mem[VAR]) is stored at memory location 2000 (hexadecimal). The variable VAR is located at memory address 3004 (hex), and contains the value 0050 (hex). The initial value of register R3 is 00A0 (hex). How many memory accesses are required to execute this instruction (assuming instructions are stored in memory), and what will be the content of the Program Counter (PC) after the instruction is fetched? Each instruction is 32 bits wide.
a) 1, 2004
b) 2, 2004
c) 1, 2002
d) 2, 3004
These are Computer Architecture and Organization Week 1 Answers
Question 4. Consider a 32-bit machine where an instruction SUB R4,R5 is stored at memory location 300C (in hexadecimal). What will be the value of MAR, MDR, IR, and PC during the execution of the instruction? Assume each instruction is 32 bits wide.
a) MAR = 300C, MDR = SUB R4, R5, IR = SUB R4, R5, PC = 3010
b) MAR = 300C, MDR = SUB R4, R5, IR = SUB R4, R5, PC = 300E
c) MAR = 3010, MDR = SUB R4, R5, IR = SUB R4, R5, PC = 300C
d) MAR = 3010, MDR = SUB R4, R5, IR = SUB R4, R5, PC = 300E
These are Computer Architecture and Organization Week 1 Answers
Question 5. Consider the following three instructions stored in memory in consecutive memory locations:
MOV R4, R5
AND R6, R4
OR R6, R5
The first instruction is stored at memory location 9000 (in hexadecimal).
Assume the following initial register values:
R4 = 00 (hex)
R5 = 40 (hex)
R6 = 3C (hex)
All instructions are 32 bits in size.
What will be the final values of R4, R6, and PC after executing all the three instructions?
a) R4 = 00, R6 = 40, PC = 9008
b) R4 = 40, R6 = 40, PC = 900D
c) R4 = 40, R6 = 00, PC = 900C
d) R4 = 3C, R6 = 01, PC = 900C
These are Computer Architecture and Organization Week 1 Answers
Question 6. A memory module has 1024 locations, each storing 16-bit data. What will be the binary address of the 513th location?
a) 100000001
b) 100000000
c) 011111111
d) 010000000
Question 7. A computer has 128 MB (megabytes) of memory, where each word is 32-bit. How many bits are needed to address any single word in memory? (Assume that the memory is word-addressable.)
a) 26
b) 25
c) 24
d) 23
These are Computer Architecture and Organization Week 1 Answers
Question 8. Which of the following statements is/are true regarding Von Neumann and Harvard architectures?
a) In Von Neumann architecture, both data and instructions share the same memory and bus.
b) In Harvard architecture, data and instructions are stored in separate memory modules.
c) In Harvard architecture, a single bus is used for both instruction fetch and data access.
d) Von Neumann architecture allows parallel access to data and instructions.
Question 9. Which of the following statements is/are true regarding instruction execution in a basic processor?
a) The Program Counter (PC) holds the address of the next instruction to be executed.
b) The Instruction Register (IR) holds the memory address of data operands.
c) The Memory Address Register (MAR) holds the address of the memory location to be accessed.
d) The Control Unit decodes the instruction stored in IR and issues control signals.
e) The Arithmetic Logic Unit (ALU) fetches instructions from memory and decodes them.
Question 10. Suppose that the following expression is evaluated on a stack architecture-based computer system: X = (P - Q) + (R * S) The number of PUSH instructions required in the equivalent assembly code will be
a) 4
b) 5
c) 6
d) 7
These are Computer Architecture and Organization Week 1 Answers
