Computer Architecture and Organization Week 4 Answers Nptel
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Computer Architecture and Organization Week 4 Answers (July-Dec 2025)
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Question 1. Which of the following hexadecimal memory addresses are valid starting points for a MIPS instruction?
a) 100A 4004
b) 1008 5005
c) 100C 6008
d) 100D 700A
e) 100E 8000
Question 2. What is the primary function of the Program Counter (PC) in a processor’s control unit?
a) It holds the address of the next instruction to be fetched and executed.
b) It stores the instruction that is currently being executed.
c) It decodes the instruction to generate control signals.
d) It stores the result of an ALU operation temporarily.
Question 3. For the single-bus organization presented, how many bus transfer cycles are required to execute the instruction MOVE R1, R2?
a) 3
b) 4
c) 5
d) 6
Question 4. For the three-bus organization shown in the slides, how many bus transfer cycles are required to execute the instruction SUB R1, R2, R3?
a) 3
b) 7
c) 5
d) 4
Question 5. In a processor with a single internal bus, which control signals must be activated to transfer the content of register R1 to register R2?
a) R1in and R2out
b) R2in and R2out
c) R1out and R2in
d) R1in and R1out
Question 6. Consider the interface for connecting a memory unit to the internal processor bus. To perform a memory read operation and transfer the data to the internal bus, which sequence of control signals is correct?
a) MDRinE followed by MDRout
b) MDRin followed by MDRoutE
c) MDRout followed by MDRinE
d) MDRoutE followed by MDRin
Question 7. The control sequence for the instruction LOAD R1, LOCA (R1 = Mem[LOCA]) is partially shown below. What is the missing action in step 5?
T1: PCout, MARin, Read, Select4, Add, Zin
T2: Zout, PCin, Yin, WMFC
T3: MDRout, IRin
T4: Address field of IRout, MARin, Read
T5: ?
T6: MDRout, R1in, End
a) Yin, R1out
b) Read, Select
c) WMFC
d) Zin, Add
Question 8. Which of the following statements is/are true for a microprogrammed control unit?
a) It is generally faster than a hardwired control unit.
b) The control logic is implemented using fixed logic circuits (gates, flip-flops).
c) It is more flexible, and new instructions can be added by updating the microprogram in the control store.
d) It uses a program stored in a control memory to generate control signals.
These are Computer Architecture and Organization Week 4 Answers Nptel
Question 9. What is the primary advantage of diagonal micro-instruction encoding over pure horizontal or vertical encoding?
a) It offers the absolute maximum parallelism possible.
b) It requires the smallest possible control word size.
c) It provides a trade-off, reducing word size from horizontal encoding while supporting the required level of parallelism.
d) It eliminates the need for decoders entirely.
Question 10. In the MIPS 5-stage instruction cycle (IF, ID, EX, MEM, WB), during which stage is the effective address for a memory load/store instruction typically calculated?
a) ID: Instruction Decode
b) EX: Execution/Effective Address Calculation
c) MEM: Memory Access
d) WB: Register Write-back
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These are Computer Architecture and Organization Week 4 Answers Nptel