Hardware Modeling using Verilog Nptel Week 5 Answers
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Hardware Modeling using Verilog Nptel Week 5 Answers (July-Dec 2025)
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Question 1. A Verilog test bench is used for:
a. Synthesis of a Verilog module.
b. Formal verification of a Verilog module.
c. Simulation of a Verilog module.
d. None of these.
Question 2. Given the following Verilog code segment for simulating primitive OR gate operation:
module or_gate;
reg a, b;
wire f;
or ggg (f, a, b);
initial begin
$dumpfile ("gate_response.vcd");
$dumpvars (0, or_gate);
$monitor ("f = %b", f);
#0 a = 0; b = 0;
#5 a = 0; b = 1;
#5 a = 1; b = 0;
#5 a = 1; b = 1;
end
endmodule
The value of the variable f will be printed number of times.
Question 3. Simulating the above module using the test bench defined in Q.2, which of the following set of variables will be dumped in “gate_response.vcd” file?
a. {x, y, out}
b. {a, b, f}
c. {x, y, out, a, b, f}
d. {f}
These are Hardware Modeling using Verilog Nptel Week 5 Answers
Question 4. Which of the following statement(s) is/are true for the “initial” block in a test bench?
a. It is executed only once.
b. It is executed repeatedly.
c. It is executed repeatedly until the end of simulation time is reached.
d. None of these.
Question 5. Consider the following Verilog code:
and #6 G1 (t1, A, B);
or #18 G2 (t2, C, ~B, D);
nor #11 G3 (t3, E, F);
nand #5 G4 (Y, t1, t2, t3);
If all the inputs A, B, C, D, E and F are fed with some logic value at the same time, after a delay time unit the correct logic value at the output port Y of nand gate will be observed.
Question 6. Which of the following(s) is/are the features of combinational circuits?
a. Output of the circuit depends on the present inputs and present state.
b. Output of the circuit depends only on the present inputs.
c. At any instance of time the circuit must be in one of the finite states.
d. None of these.
Question 7. Which of the following statement(s) is/are true about Verilog test benches?
a. A test bench may contain more than one initial blocks.
b. A test bench may contain both initial and always blocks.
c. Input and output ports of the DUT require explicit connections to the test bench module.
d. All of these.
These are Hardware Modeling using Verilog Nptel Week 5 Answers
Question 8. Which of the following is/are true about the following Verilog directive
`timescale 10ns / 10ps
a. The synthesis tool interprets 10 nanoseconds as unit of delay.
b. The directive is only considered during simulation and ignored during actual synthesis.
c. The simulator interprets 10 nanoseconds as unit of delay with a resolution of 10 picoseconds.
d. All of these.
Question 9. What will be the time period of the clock (clk) generated by the following code segment?
module test_dut;
reg clk;
initial
#2 clk = 1'b0;
always
#4 clk = ~clk;
endmodule
a. 6 time units
b. 2 time units
c. 8 time units
d. None of these
Question 10. Which of the following statements is/are true?
a. For both Mealy and Moore machines the present state and present input determines the next state.
b. In Mealy machine the output is associated with present state.
c. In Moore machine the output is associated with present state and present input.
d. Both Mealy and Moore machines are used to realize sequential circuit.
These are Hardware Modeling using Verilog Nptel Week 5 Answers