Computer Architecture Week 4 Assignment Nptel Answers 2024
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Computer Architecture Nptel Week 4 Assignment Answers (July-Dec 2024)
Q1. Consider the following ARM assembly instruction.
ldr r1, [r0] If the value obtained from the address stored in r0 is v, then we need to fetch the bytes from _ to __ from memory and save them in r1.
v to v+4
v to v+3
v+1 to v+4
None of the options
Answer: v to v+3
Q2. In the ARM ISA, we have a/an _ bit to specify if the return address needs to be saved or not for branch instructions.
L (Link)
S (Status)
I (Instruction)
None of the options
Answer: L (Link)
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These are Computer Architecture Nptel Week 4 Assignment Answers
Q3. The x86 ISA has _ floating-point registers and the register _ is always the top of the stack.
8, st0
8, st7
16, st0
16, st7
Answer: 8, st0
Q4. In the ARM ISA, the effective memory address is computed after updating the base address in the __ addressing mode (with auto update).
pre-indexed
post-indexed
register-indirect
None of the options
Answer: post-indexed
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These are Computer Architecture Nptel Week 4 Assignment Answers
Q5. In the x86 processor, the local descriptor table (LDT) is typically local to a __.
process
program
user
None of the options
Answer: process
Q6. In the x86 ISA, the fixed offset used while specifying the effective address of a memory operand, is known as the __.
displacement
scaled index
base address
None of the options
Answer: displacement
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These are Computer Architecture Nptel Week 4 Assignment Answers
Q7. The x86 ISA is a __ ISA.
CISC
RISC
VLIW
None of the options
Answer: CISC
Q8. In the x86 ISA, if the memory operand of an instruction is of the form [eax + ecx*2], then the addressing mode is __.
base-scaled-index
base-scaled-index-offset
base-offset
None of the options
Answer:base-scaled-index
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These are Computer Architecture Nptel Week 4 Assignment Answers
Q9.Which of the following statements is incorrect for the x86 ISA?
Both the operands can be a register
At most one of the operands can be a memory location
Both the operands can be an immediate value
None of the options
Answer:Both the operands can be an immediate value
Q10. In the ARM ISA, the bl instruction saves the return address into the __ register.
lr
sp
fp
ip
Answer: lr
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These are Computer Architecture Nptel Week 4 Assignment Answers
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