Computer Architecture Nptel Week 9 Assignment Answers 2024

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Computer Architecture Nptel Week 9 
Assignment Answers image
Computer Architecture Nptel Week 9 Assignment Answers

Computer Architecture Nptel Week 9 Assignment Answers (July-Dec 2024)


  1. The last stage of a 5-stage SimpleRISC processor is the __.
    A) Instruction fetch stage
    B) Operand fetch stage
    C) Register write stage
    D) Memory access stage

Answer: C) Register write stage


  1. The data path does not consist of a/the __.
    A) Register File
    B) Memory
    C) ALU
    D) None of the options

Answer: D) None of the options


  1. The __ stage of a 5-stage SimpleRISC processor executes a load or store instruction.
    A) Operand Fetch (OF)
    B) Execute (EX)
    C) Memory Access (MA)
    D) Register Write (RW)

Answer: C) Memory Access (MA)


  1. What is the value of the isBranchTaken control signal for the ret instruction? Choose the most appropriate answer.
    A) 1
    B) 0
    C) 1 if the branch is taken (conditional)
    D) 0 if the branch is not taken (conditional)

Answer: A) 1


  1. The __ path consists of all the elements in a processor that are dedicated to storing, retrieving, and processing data.
    A) Control
    B) Data
    C) Memory
    D) Register

Answer: B) Data


  1. In horizontal microprogramming, the total size of the encoded instruction is _ bits.
    A) 65
    B) 43
    C) 32
    D) 40

Answer: A) 65


  1. The _ microinstruction makes the μcontrol unit wait for one cycle and populates all the decode registers in this cycle.
    A) mLoadIR
    B) mLoad
    C) mDecode
    D) mb
See also  Computer Architecture Week 3 Assignment Nptel Answers 2024

Answer: C) mDecode


  1. __ microprogramming requires a decode stage for generating all the control signals.
    A) Vertical
    B) Horizontal
    C) Data
    D) None of these

Answer: A) Vertical


  1. The __ control signal decides whether the instruction writes to a register or not.
    A) isImmediate
    B) isWb
    C) isSt
    D) isLd

Answer:B) isWb


  1. Which of the following functions are performed by the operand fetch unit of a 5-stage SimpleRISC processor? Choose the most appropriate option.
    A) Fetch the register operands from the register file
    B) Generate control signals
    C) Decode the instruction
    D) All of the options

Answer: D) All of the options


These are Computer Architecture Nptel Week 9 Assignment Answers

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