These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q1. Loop unrolling results in increasing register pressure decreasing I cache miss increasing number of control hazards increasing control dependence
Answer: increasing register pressure
Q2. In Tomasulo’s algorithm, register renaming is done using Compiler scheduling Reservation Station Reorder Buffer Common Data Bus
Answer: Reservation Station
These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q3. Which one of the following statements is FALSE? Compiler can achieve instruction level parallelism using strip mining. A normal in-order multi cycle MIPS pipeline can never achieve an IPC larger than 1. In a MIPS multi-cycle floating point pipeline that supports operand forwarding, there will be six stalls between a pair of adjacent MUL instructions that has a RAW dependency between them. WAW and WAR are true data dependencies.
Answer: WAW and WAR are true data dependencies.
Q4. Register Renaming can solve WAR and WAW hazards RAW hazard only WAR hazard only RAW, WAR, and WAW hazards
Answer: WAR and WAW hazards
These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q5. Which of the following is the best match from Set A to Set B? Set A Set B W. Static Scheduling 1. Reorder buffer X. Operand Forwarding 2. Loop unrolling Y. Speculative Dynamic Scheduling 3. RSI Update Z. CDB writing 4. Reservation station W→3 X→1 Y →4 Z → 2 W→2 X→4 Y→1 Z → 3 W→2 X→4 Y→3 Z → 1 W→3 X→2 Y→1 Z → 4
Answer: W→2 X→4 Y→1 Z → 3
These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q6. In a dynamically scheduled processor that supports speculation, if the register status indicator of a register Rx is 0, then the latest value of Rx can be obtained from the entry #0 in the re-order buffer. the latest value of Rx will be produced by functional unit #0. the latest value of Rx can be obtained from the entry #0 in the reservation station. the latest value of Rx is available in the Register File.
Answer: the latest value of Rx is available in the Register File.
These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q7. Consider an ADD instruction with first operand as Rx and second operand as Ry that is to be executed in a dynamically scheduled processor that follows Tomasulo’s algorithm. When the instruction is issued, the seven-tuple entry {Op, Qj, Qk, Vj, Vk, A, Busy} in the reservation station for this instruction is {ADD, 2, 0, 0, 2, A, 1}. Which of the following information is correct about the operands of this ADD instruction? Rx value is available from output of functional unit #2 and Ry value is available from output of functional unit #0. Rx value is 2 and Ry value is available from output of functional unit #0. Rx value is available from output of functional unit #2 and Ry value is 2. Rx value is 2 and Ry value is 0.
Answer: Rx value is available from output of functional unit #2 and Ry value is 2.
These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q8. Suppose, a load and a store access the same address. If in program order the store appears before the load, interchanging them in execution order can create __ hazard. RAW WAR WAW No
Answer: RAW
These are Multi-Core Computer Architecture Nptel Week 4 Answers
Q9. Consider an instruction pipeline with an issue width of 1 that uses Tomasulo’s algorithm with one reservation station per functional unit. There is one Integer MUL unit, one Integer DIV unit, and one Integer ADD unit, all connected to a single CDB. The functional units are not pipelined. An instruction waiting for data on CDB can move to its EX stage in the cycle after the CDB broadcast. The instructions are: I1: ADDI R1, R1, #8 I2: DIV R3, R2, R1 I3: MUL R4, R1, R3 I4: DIV R5, R4, R1 Assume the following information about functional units. Functional unit type Cycles in EX stage Integer MUL unit 4 Integer DIV unit 8 Integer ADD unit 1 In which cycle does instruction I3 write to CDB?
